As the integrated circuit art has advanced, more and more circuit devices, and consequently more and more circuit functions, have been placed on single chips. These developments have posed problems with regard to the testing Of such chips. For example, while testing of even an extremely large memory array chip may be relatively straightforward, a chip that integrates various different kinds of functions, including an embedded memory array and logic, may pose problems for the circuit designer/tester who desires adequate testability of the embedded structures. For example, such embedded memory arrays typically have far fewer input/output (I/O) pins available to the circuit tester than a memory array occupying a stand alone chip. The problems associated with testing embedded memory arrays extend also to embedded logic functions.
A general solution to the above-described problem is to embed test circuitry on the chip itself. Such schemes are frequently referred to as Built-In Self-Test ("BIST") or Array Self-Test ("AST"). Hereinafter, such arrangements are referred to generically as BIST circuits. These circuits are well known in the art; for example, reference commonly assigned U.S. Pat. No. 5,173,906, entitled "Built-In Self-Test For Integrated Circuits."
Also, to alleviate access requirements device manufacturers have designed components that include so-called "scan circuitry" in addition to the circuitry required for normal operation in functional mode of the component. The scan facility enables such chip components to switch from ordinary operation into a "scan" mode used for testing. This facility enables a tester to take a "snapshot" of the signals at nodes within the integrated circuit where physical access would otherwise be difficult or impossible.
One type of scan organization is known as "boundary" scan because the nodes with which the scan circuitry is associated are input and output ports used in normal component operations; the nodes are thus in a sense on the "boundary" of the circuit to be tested. When such components have been switched from normal operation to scan mode, boundary scan latches can not only be loaded and read serially, but can also be caused both to receive and transmit data in parallel. By using the boundary-scan facility, one can effectively apply and sense signals at all scan-component terminals by direct physical access to the input and output ports of a component. Details of a standard approach to boundary-scan operation are described in IEEE Standard 1149.1, which sets forth a set of accepted operational parameters and definitions for boundary-scan components.
Existing circuit test methodologies have often employed boundary scan latches between memory blocks, between memory and logic, and between multiple logic blocks. Separation between blocks is usually made at cycle boundaries to allow efficient single cycle testing to take place from the scan chain, which in most cases is a viable approach. However, in certain designs the separation of logic and memory can prove to be costly because of performance degradation and increased area consumption on the chip. Further, in the case of Content Addressable Memory (CAM), where the memory cell and XNOR gate of a comparator are physically coupled, the introduction of boundary latches between the memory and logic is impossible.
Comparator logic embedded at an output of a memory array is becoming more and more common. Faster cycle times and increased operations per cycle require that boundary scan latch placement be minimized. For example, boundary latches between the output of a memory array and one input to a wide comparator logic circuit cannot be accomplished while still accommodating a cycle time of only several nanoseconds. The addition of a boundary scan latch at the memory array/comparator logic interface would require an additional cycle for the logic to be evaluated due to the data transition through the latch, thereby severely impacting machine performance. Further, with wide comparator logic, for example, 288 bits wide, the addition of a corresponding number of boundary scan latches would utilize a significant area of the semiconductor device. Additionally, testing time would be very high for such circuitry. To minimize testing time, comparator logic has typically been broken into discrete logic sections. Unfortunately, this might require a comparator design which includes additional boundary scan latches, thereby further degrading performance.
Thus, a need exists in the semiconductor art for a test structure and corresponding test method which do not employ scannable boundary latches between the memory array and subsequent logic circuit, while still achieving 100 percent test confidence of the subsequent logic circuit, preferably in a minimum number of cycles.